The present invention relates generally to semiconductor manufacturing and more specifically to integrated circuit manufacturing using silicon-based, low dielectric constant materials and chemical vapor deposition equipment.
Silicon compounds, such as silicon dioxide, that can be used as coatings are particularly valuable on electronic substrates. Such coatings serve as protective coatings, inter-level dielectric layers, doped dielectric layers to produce transistor-like devices, multilayer devices, etc.
Unfortunately, development of high integration and high-density very large scale integrated circuits has progressed so rapidly that earlier silicon compounds have become less than satisfactory. The reductions in size have been accompanied by increases in switching speed of such integrated circuits, and this has increased the problems due to capacitance coupling effects between closely positioned, parallel conductive channels connecting high switching speed semiconductor devices in these integrated circuits. This has necessitated a change from using silicon dioxide, which has a dielectric constant in excess of 4.0, to the use of lower dielectric constant materials.
The combination of high density and submicron geometries has also lead to the surfaces of semiconductor substrates having relatively large protrusions and depressions with small spaces in between. This has posed serious problems for fabrication technology because of the difficulty of providing uniform depositions and subsequently planarizing such surfaces. One answer has been to use dielectrics which are deposited on the silicon wafer in liquid form. By spinning on dielectric films in a liquid form followed by a series of soft bakes and a hard bake to cause solvent evaporation and curing, a high degree of uniformity and planarization have been achievable.
The soft bakes are performed on three different heating elements with a robot arm moving the silicon substrates from one heating element to another. The dielectric film-coated silicon substrates are heated at various temperatures for short periods of time. For example, for HSQ (hydrogen silsesquioxane) 60 seconds at 150xc2x0 C. causes solvent evaporation. Then at 200xc2x0 C. it causes reflow into the wafer""s channels, and then at 350xc2x0 C. it causes slight cross-linking. This prevents curing of the dielectric film before the solvent evaporates. The hard bake cure in an oven in a nitrogen gas ambient at 400xc2x0 C. for an hour cures the HSQ.
The materials that have been used for the spun on dielectric films have included various organic silicon compounds in liquid solvents. These organic silicon compounds have included BCB (benzocyclobuten), TBOS (tetraethoxysilane), TMOS (tetramethoxysilane), OMCTS (octamethyleyclotetrasiloxane), HMDS (hexamethyldisiloxane), SOB (trimethylsilil borxle), DADBS (diaceloxyditerliarybutoxsilane), and SOP (trimethylsilil phosphate). And the fluid carrier would be a solvent such as MIBK (methyl isobutyl ketone) or mesitylene (1,3,5 trimethol benzene). One of the more commonly used silicon-based, low dielectric constant materials is HSQ (hydrogen silsesquioxane) in MIBK solvent.
Unfortunately, these organic materials tend to be difficult to planarize and often react chemically to the photoresists used in the photolithographic processes required to create the interconnects for the transistors and other elements of an integrated circuit. This means that the dielectric films must be covered, or capped, by another material after baking and curing. Cap layers are also used as etch hard masks or chemical-mechanical polishing (CMP) stop layers in the damascene process.
It has been found that a good capping material is silicon dioxide, SiO2, silicon nitride, SiN, or SiON, silicon oxynitride. However, this requires the dielectric film-coated silicon wafer to be transferred from the oven to deposition apparatus, such as chemical vapor deposition (CVD) equipment, for deposition of the capping material. After capping, the wafer must be transferred for planarization by CMP before being transferred to the photolithographic processing equipment and other equipment for the deposition of a level of interconnects.
The above steps must then be repeated for additional levels of dielectrics and interconnects. Currently, five levels are common, but many more levels are projected in the future.
As well known in the art, there are numerous problems with the above system. Not only are there long delays between steps, but the system is subject to particle and surface contamination on the dielectric films during each of the transfers. In addition, the multiple transfers afford opportunity for possible breakage, many tools are required, and the cycle process time is long. All of these mean that the process is quite expensive.
The present invention provides an apparatus and method in which drying and curing of a low dielectric constant film on a silicon wafer, and subsequent capping of the film, is done in-situ in chemical vapor deposition equipment.
The present invention further provides an apparatus and method for shortening the process time for manufacturing semiconductors requiring inter-level dielectric and interconnect layers.
The present invention further provides an apparatus and method for eliminating the queue time between processing steps.
The present invention provides an apparatus and method for eliminating transfers between baking and capping.
The present invention still further provides an apparatus and method for reducing particles and contamination on the low dielectric constant material before capping.
The present invention still further provides an apparatus and method which results in better adhesion between the low dielectric constant film and the capping layer.
The present invention still further provides an apparatus and method for making the above improvements extend from spinning on the low dielectric constant film to completion of the chemical vapor deposition of the capping material.